Open a terminal, enter the folder and run the script: cd / home / user / vhdl sh compile.sh

To avoid wasting time compiling command by command while working on the program, we save a file called compilar.sh with the following content in the same folder: ghdl -a lou.vhd & ghdl -a aru.vhd & ghdl -a muxVector.vhd & ghdl -a aluComponente.vhd & ghdl -e aluComponente & ghdl -r aluComponent -vcd = alu&componente.wave U1: lou PORT MAP (A, B, process, LOU output) U0: aru PORT MAP (A, B, process, ARU exit) Signal output: std_logic_vector (7 DOWNTO 0) Signal process: std_logic_vector (3 DOWNTO 0) SIGNAL outputLOU: std_logic_vector (7 DOWNTO 0) SIGNAL outputARU: std_logic_vector (7 DOWNTO 0) Process: IN std_logic_vector (3 DOWNTO 0) PORT (op1: IN std_logic_vector (7 DOWNTO 0) Output <= from ARU when '0', from LOU when others ДЄLU Component (aluComponent.vhd) LIBRARY ieee USE IEEE.STD_LOGIC_1164.all USE IEEE.NUMERIC_STD.all ДЄRCHITECTURE inputs_aluComponent OF aluComponent IS Output: out std_logic_vector (7 DOWNTO 0)) PORT (from ARU: IN std_logic_vector (7 DOWNTO 0) ДЇromLOU: IN std_logic_vector (7 DOWNTO 0) Multiplexer (muxVector.vhd) LIBRARY ieee USE IEEE.STD_LOGIC_1164.all USE IEEE.NUMERIC_STD.all To do this, we will create a component that uses the previous block and we will specify the signals. Now we will need to create the signals for the simulation. vhd so that Geany will recognize the format and color the reserved words. Don't forget to save the program with the extension.

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